• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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  • 法律状态
  • 优先权
    • 专利摘要:
    A ferroelectric transistor suitable as a storage element comprises a first gate intermediate layer 13 and a first gate electrode 14 between the source-drain region 12 on the surface of the semiconductor substrate 11 and includes a first gate intermediate layer ( 13 includes at least one ferroelectric layer 132. A second gate intermediate layer 16 and a second gate electrode 17 are disposed beside the first gate intermediate layer 13 between the source-drain-regions 12, and the second gate intermediate layer 16 forms a dielectric layer. Include. The first gate electrode 14 and the second gate electrode 17 are connected to each other by a diode structure.
    公开号:KR20010074987A
    申请号:KR1020017002945
    申请日:1999-07-05
    公开日:2001-08-09
    发明作者:토마스 페터 한네더；한스 라이징어；라인하르트 슈텡글；하랄트 바흐호퍼；헤르만 벤트；볼프강 횐라인
    申请人:추후제출；인피니언 테크놀로지스 아게；
    IPC主号:
    专利说明:

    FERROELECTRIC TRANSISTOR, ITS USE IN A STORAGE CELL SYSTEM AND ITS METHOD OF PRODUCTION}
    [2] It is known that ferroelectric transistors are used as storage cells in storage cell systems (see for example T. Nakamura, Y. Nakao, A, Kamisawa, H, Takasu: A Signal Transistor Ferroelectric Memory Cell, IEEE, ISSCC, 1995, pages 68-69). Reference). In this case, each ferroelectric transistor is connected between the supply voltage line and the bit line. Selection is made through the back gate. The ferroelectric transistor used in this case comprises a floating gate electrode between the ferroelectric layer and the gate oxide, the load of which is controlled through the polarization state of the ferroelectric layer.
    [3] When reading information, it has been shown that the voltage drops even in unselected storage cells, which can cause errors in the information stored in individual storage cells. The error is attributed to the fact that the domain polarization alignment process in ferroelectric materials is statistically characteristic and can be caused even at low pressures.
    [1] The present invention relates to a ferroelectric transistor comprising two source- / drain-regions, a channel region and a gate electrode, wherein a layer of ferroelectric material is provided between the gate electrode and the channel region. The conductivity of the transistor depends on the polarization state of the layer made of ferroelectric material. Ferroelectric transistors of this type are studied in terms of nonvolatile memory. In this case two different polarization states of the layer of ferroelectric material are assigned to two different logic values of the digital information. A further use for ferroelectric transistors in this manner is, for example, the Nullal network.
    [26] 1 shows a cross-sectional view of a ferroelectric transistor.
    [27] 2 shows a cross-sectional view of a ferroelectric transistor, including a dielectric layer through which the first gate intermediate layer and the second gate intermediate layer pass.
    [28] 3 to 5 show the manufacturing steps of the ferroelectric transistor shown in FIG.
    [29] 6 shows a circuit sketch for a storage cell system.
    [4] It is an object of the present invention to provide a ferroelectric transistor which is suitable as a storage cell of a storage system and which prevents alteration of the recorded information during the reading process. It should also be provided with a process for its preparation.
    [5] The object is achieved by a ferroelectric transistor according to claim 1 and a method of manufacturing the ferroelectric transistor according to claim 11. Further embodiments of the invention appear in the remaining claims.
    [6] The ferroelectric transistor includes two source- / drain-regions disposed in a semiconductor substrate. As semiconductor substrates all semiconductor materials, in particular single crystal silicon, are suitable. In this case, the semiconductor substrate may be a single crystal silicon plate, or an SOI substrate.
    [7] A first gate interlayer and a second gate electrode are disposed on the surface of the semiconductor substrate between the two source- / drain-regions, and the first gate interlayer includes at least one ferroelectric layer. A second gate intermediate layer and a second gate electrode are disposed between the source / drain regions in the connecting line direction between the source / drain regions, and the second gate intermediate layer is a dielectric layer. It includes. The first gate electrode and the second gate electrode are connected to each other through a diode structure.
    [8] A first gate electrode and a second gate electrode are disposed side by side along the connection line between the source / drain regions in the ferroelectric transistor. Therefore, the channel region of the ferroelectric transistor is divided, and a first portion of the channel region disposed below the first gate electrode is controllable by a load acting on the first gate electrode, and The second portion of the channel region disposed below is controllable by a load acting on the second gate electrode. Only when the first portion of the channel region disposed below the first gate electrode and the second portion of the channel region disposed below the second gate electrode are electrically conductive, a current flows between the source / drain regions. Can flow.
    [9] The diode structure blocks the diode structure when a voltage controlling the conductivity of the channel region under the second gate electrode is applied to the second gate electrode, thereby polarizing the first gate electrode to be separated from the voltage.
    [10] When the ferroelectric transistor is used as a digital information memory, two polarization states are assigned to logic values in the ferroelectric layer. In the first polarized state, the channel region under the first gate electrode and the ferroelectric layer is conductive, but not in the second polarized state.
    [11] Since the first gate electrode and the second gate electrode are arranged side by side in the direction of the connection line between the source / drain regions, control via the second gate electrode in the reading process is sufficient. Depending on the polarization state of the ferroelectric layer, the channel region below the first gate electrode is conductive or not. By controlling the second gate electrode such that the transistor is connected to the region of the second gate electrode, information is read and an electric current flows through the transistor.
    [12] The diode structure connected between the first gate electrode and the second gate electrode is reliably set so that the voltage drops only through the second gate electrode for control of the second gate electrode. The first gate electrode is separated from the voltage through the diode structure so that no voltage drops through the ferroelectric layer. This prevents a change in polarization of the ferroelectric layer and thus a change in stored information.
    [13] Alternatively, a voltage may be applied to the second gate electrode so that the ferroelectric layer is polarized. This is used for recording and erasing information.
    [14] In this case, the recording of the information is made by a voltage which is larger than the blocking voltage of the diode structure and polarizes the ferroelectric layer in the first direction.
    [15] The erasing of the information is done by voltages with different opcodes so that the diode structure is polarized in the conductive direction and the voltage dropped on the ferroelectric layer polarizes the diode structure in the second direction.
    [16] In this regard, the concept of recording and erasing information is also used in reverse.
    [17] Preferably, the second gate interlayer and the second gate electrode are each composed of two substructures arranged in reflection symmetry with respect to the first gate interlayer. The two partial structures of the second gate electrode are electrically connected to each other. The shape has the advantage that the voltage applied to the second gate electrode causes the electric field of the scheme in a read operation, that the ferroelectric layer is provided on the equipotential line, so that no change in the polarization of the ferroelectric layer occurs. This shape of the invention is particularly insensitive to failure.
    [18] Preferably, a dielectric layer is provided between the surface of the semiconductor substrate and the ferroelectric layer to facilitate deposition of the ferroelectric layer.
    [19] In terms of manufacturing a ferroelectric transistor, a dielectric layer disposed in the second gate intermediate layer between the semiconductor surface and the ferroelectric layer, and a dielectric layer that is a component of the second gate intermediate layer, have a stack of ferroelectric layers and first gate electrodes formed on the surface thereof. It is preferably formed of a penetrating electrical layer.
    [20] Preferably said first gate electrode and / or second gate electrode is part of a diode structure. In this way the required space of the diode structure is reduced.
    [21] Preferably, the first gate electrode comprises polycrystalline silicon doped with a first conductivity type. The second gate electrode likewise comprises single crystal silicon doped with a second conductivity type opposite to the first conductivity type. In this case, since the first gate electrode is adjacent to the second gate electrode, the diode structure is formed of the first gate electrode and the second gate electrode. In this configuration only three terminals are required for the operation of the ferroelectric transistor, two of which are connected to the source / drain region and the other to the second gate electrode. Alternatively in this shape the first gate electrode and the second gate electrode may each be formed of corresponding doped epitaxially grown silicon.
    [22] For technical reasons it is preferred that an auxiliary layer, for example platinum, is provided between the ferroelectric layer and the first gate electrode. The auxiliary layer prevents undesirable properties of the ferroelectric layer, such as for example fatigue or imprint resistance.
    [23] The first gate interlayer in the present invention comprises a dielectric layer consisting of CeO 2 , ZrO 2 , Y 2 O 3 or an additional oxide with a high dielectric susceptibility as possible, such as SiTiO 3 . As the dielectric layer in the second gate interlayer, in particular SiO 2 , CeO 2 , ZrO 2 , Y 2 O 3 or further oxides with as high dielectric susceptibility as possible, such as SiTiO 3, are suitable. The ferroelectric layer may in particular consist of strontium-bismuth-tantalate (SBT), lead-zirconium-titanate (PZT), lithium-niobium acid salt (LiNbO 3 ) or barium-strontium-titanate (BST).
    [24] The ferroelectric transistor is preferably usable as a storage cell in a storage cell system. In this case, it is desirable to provide a selection transistor having a control electrode in addition to the ferroelectric transistor in each storage cell in view of preventing failure of the storage cell system in reading, writing and erasing information. The storage cell system also includes a word line, a bit line and a supply line, wherein the word line traverses the supply line and the bit line. One ferroelectric transistor of each of the storage cells is connected between two adjacent bit lines. The selection transistor is connected between two gate electrodes and one of the supply voltage lines. Control electrodes of the selection transistors are each connected to one of the word lines.
    [25] The invention is next described in more detail by examples and figures.
    [30] Two source- / drain-regions 12 are disposed in a p-doped semiconductor substrate 11 made of single crystal silicon. The first gate intermediate layer 13 and the first gate electrode 14 are disposed on the surface of the semiconductor substrate 11 between the source / drain region 12 (see FIG. 1). The first gate intermediate layer 13 has a size smaller than the size corresponding to the gap between the source / drain regions 12 in the direction of the connection line between the source / drain regions 12. The first gate intermediate layer 13 includes a first dielectric layer 131 and a ferroelectric layer 132. The first dielectric layer 131 includes CeO 2 and has a thickness of 5 to 10 nm. The ferroelectric layer 132 has a thickness of 50 to 100 nm and includes strontium-bismuth-tantalate (SBT), or lead-zirconium-titanate (PZT). The first gate electrode 14 is formed of p + -doped polysilicon having a thickness of 30 to 50 nm and having a dopant concentration of several 10 19 cm -3 . An auxiliary layer 15 is disposed between the first gate electrode 14 and the ferroelectric layer 132, which is used to protect the ferroelectric layer 132 and is formed of platinum to a thickness of 30 nm.
    [31] On the side of the first dielectric layer 131, a second dielectric layer 16 of 5 to 10 nm thickness made of SiO 2 is disposed. The second dielectric layer 16 consists of two parts, the first part being disposed between the first of the source- / drain-areas 12 and the first dielectric layer 131, and the second part being the source. Disposed between the second of the-/ drain-regions 12 and the first dielectric layer 131. Two portions of the second dielectric layer 16 are disposed symmetrically with respect to the first dielectric layer 131. Two portions of the second dielectric layer 16 act as second gate intermediate layers. On top of the second dielectric layer 16 is a second gate electrode 17 made of n + -doped polysilicon. As the second gate electrode 17 covers the first gate electrode 14, the second gate electrode has a U-shaped cross section in the cross section shown in FIG. 1. As a result, the two portions of the second gate electrode 17 arranged on the surface of the two portions of the second dielectric layer 16 are electrically connected to each other. In addition, the second gate electrode 17 is adjacent to the surface of the first gate electrode 14. The second gate electrode 14 and the second gate electrode 17 form a common diode structure.
    [32] To write information to the ferroelectric transistor, the pn-junction formed by the first gate electrode 14 and the second gate electrode 17 operates in the conducting direction. This means that a negative voltage pulse is applied to the n + -doped second gate electrode 17. As a result, the ferroelectric layer 132 is polarized such that a portion of the channel region disposed under the first gate intermediate layer 13 accumulates and is thus blocked.
    [33] For the reading of the storage transistor, the pn-junction formed by the first gate electrode 14 and the second gate electrode 17 is operated in reverse at the breakdown voltage in the non-conductive direction. As a result, both sides of the ferroelectric layer 132 of the channel region are inverted through the second gate electrode 17 without changing the polarization state of the ferroelectric layer 132. Current flows through the transistor only when the ferroelectric layer 132 is polarized so as to be inverted even under the first gate interlayer 13, ie, in the portion of the channel region located below the ferroelectric layer 132. Otherwise, no current flows through the transistor. Thus, states such as "current flow through transistor" or "non-current flow through transistor" are assigned to different logic information.
    [34] In order to erase the information stored in the ferroelectric layer 132, a pn-junction formed of the first gate electrode 14 and the second gate electrode 17 is operated above the breakdown voltage in the non-conductive direction. As a result, the ferroelectric layer 132 is polarized such that the channel region under the first gate intermediate layer 13 is inverted and thus electrically conductive.
    [35] In a further embodiment (see FIG. 2), the semiconductor substrate 21 includes two source- / drain-regions 22, which are formed similarly as described by FIG. 1. A dielectric layer 26 having a layer thickness of 5 to 10 nm and formed of CeO 2 or ZrO 2 is disposed on the surface of the semiconductor substrate 21 between the source / drain-regions 22. A ferroelectric layer 23 is disposed on the surface of the dielectric layer 26 and the cross section of the ferroelectric layer parallel to the surface of the substrate 21 is smaller than the dielectric layer 26. Dielectric layer 26 protrudes from the side of ferroelectric layer 23. The auxiliary layer 25 is disposed on the surface of the ferroelectric layer 23, and the second gate electrode 24 is disposed on the surface of the auxiliary layer 25. A second gate electrode 27 is also provided, which meets at the surface of the dielectric layer 26 on both sides of the ferroelectric layer 23 and covers the first gate electrode 24. The ferroelectric layer 23, the auxiliary layer 25, the first gate electrode 24 and the second gate electrode 27 are formed similar to that described by FIG. The manner of operation of the ferroelectric transistor shown in FIG. 2 is similar to that described by FIG. 1.
    [36] In order to fabricate the ferroelectric transistor shown in FIG. 2, a dielectric layer 26 is deposited on the surface of the semiconductor substrate 21. Active and inactive regions in the semiconductor substrate are first defined by insulating techniques, such as LOCOS- or Shallow Trench Isolation (STI) techniques (not shown), and walls are implanted in a known manner (not shown). Ferroelectric layer 23 is deposited on dielectric layer 26 by one or multiple stages of the Sol-Gel-method or CVD-process. In order for the ferroelectric layer 23 to be provided with the desired ferroelectric phase, tempering at 700 ° C is achieved. Subsequently, an auxiliary layer 25 made of platinum is deposited on the surface of the ferroelectric layer 23 by sputtering. A p-doped polysilicon layer 24 ′ is deposited on the auxiliary layer 25 (see FIG. 3).
    [37] Then, using a photoresist mask defined in the form of the first gate electrode 24, the p + -doped polysilicon layer 24 ′, the auxiliary layer 25 and the ferroelectric layer 23 are divided into the dielectric layer 26. It is structured except for its surface. A multi-stage etching method is used for this purpose, in which HBr or HCl is used for the structuring of the p + -doped polysilicon layer 24 ', and for the structuring of the auxiliary layer 25 of the ferroelectric layer 26. For example, Cl 2 and / or Ar with additives of heavy gases such as SF 6 , BCl 3 are used.
    [38] Subsequently, an n-doped polysilicon layer 27 'having a thickness of 120-150 nm is deposited. In the subsequent multi-step etching process, the n-doped polysilicon layer 27 'and the dielectric layer 26 are structured and a second gate electrode 27 is formed. The second gate electrode 27 covers the first gate electrode 24 on both sides from the side. To structure the n-doped polysilicon layer 27 ', HBr or HCl is used, and for the structure of the dielectric layer 26, containing Cl, Ar or additives of heavy gases such as SF 6 , BCl 3 , for example. A mixture consisting of Cl and Ar is used (see FIG. 5).
    [39] The source- / drain-region 22 is then implanted so as to self-align with the second gate electrode 24 by arsenic implantation. This completes the ferroelectric transistor shown in FIG.
    [40] The manufacturing method can be changed in various ways. In particular, tempering for the fixing of a given ferroelectric phase of the ferroelectric layer 23 is characterized in that the p-doped polysilicon layer (when SiO 2 is not formed above the auxiliary layer and below the second electrode because the required temperature is sufficiently low) After the deposition of 24, or preferably after the deposition of the auxiliary layer 25. In addition, when structuring the first gate electrode 24, the dielectric layer 26 is structured together except the surface of the semiconductor substrate 21, and tempering may be performed after the formation of the first gate electrode 24. In this case, at the tempering side, on the side of the first gate electrode 24, an SiO 2 -layer is formed on the surface of the semiconductor substrate 21, and then the layer is on the second side of the first gate electrode 24. It is used as the gate oxide under the gate electrode 27. In this case, tempering is preferably performed such that the SiO 2 -layer is not simultaneously formed between the first gate electrode 24 and the auxiliary layer 25.
    [41] In addition, a source- / drain-region 22 having an LDD-profile can be formed. For this purpose, spacers are formed at the edge of the second gate electrode 27 during the process.
    [42] In the above embodiment, the configuration of the n-channel transistor is described. The invention is feasible similarly to p-channel transistors, in which case all conductivity types can be exchanged correspondingly.
    [43] A plurality of storage cells are provided in the storage cell system, wherein each one of the storage cells includes one ferroelectric transistor FT and one selection transistor AT (see FIG. 6). The ferroelectric transistor FT is implemented as described by FIG. 1 or FIG. 2, respectively. The selection transistor AT is implemented as a MOS transistor including a gate electrode. The storage cell system also includes a word line WL, a supply line VL, and a bit line BL. The word line WL crosses the bit line BL as well as the supply line VL.
    [44] The ferroelectric transistors FT of each of the storage cells are connected between two adjacent bit lines BL, respectively. The select transistor AT of the corresponding storage cell is connected between the second gate electrode of the ferroelectric transistor FT and the supply line VL. The gate electrode of the select transistor AT is connected to one of the word lines WL.
    [45] The selection of the storage cell is made via the corresponding word line WL and the corresponding supply line VL in the storage cell system.
    [46] The reading of the storage cell is made by conduction test between adjacent bit lines BL, with corresponding ferroelectric transistors FT connected therebetween. For reading of information, a voltage level is supplied to the associated supply line VL, whereby the pn-junction formed of the first gate electrode and the second gate electrode is operated below the breakdown voltage in the non-conductive direction in the ferroelectric transistor. In this case, without changing the polarization state of the ferroelectric layer, the second gate electrode locally inverts the channel region of the ferroelectric transistor on the side of the ferroelectric layer. The current passing through the ferroelectric transistor flows only if the ferroelectric layer is polarized such that it is inverted even under the ferroelectric layer of the channel region. The current between adjacent bit lines BL can only flow if the selected ferroelectric transistor FT is connected, i.e. if the ferroelectric layer is correspondingly polarized.
    [47] In order to write information to the ferroelectric transistor FT of one storage cell, a selection is likewise made through the corresponding word line WL and the corresponding supply line VL. In this case, a level for operating the pn-junction formed by the first gate electrode and the second gate electrode of the ferroelectric transistor FT in the conductive direction is supplied to the corresponding supply line VL. As a result, the ferroelectric layer is polarized such that the channel region accumulates below the ferroelectric layer and is thus blocked.
    [48] In order to erase the information in the ferroelectric transistor of one storage cell, the storage cell is likewise selected via word line WL and supply line VL. By applying a voltage level of this type to the supply line VL, the pn-junction formed of the first and second gate electrodes of the ferroelectric transistor is operated above its breakdown voltage in the non-conductive direction. As a result, the ferroelectric layer is polarized such that the channel region underneath the ferroelectric layer is reversed and thus conductive.
    [49] In the read process, the write process and the erase process, all other storage cells connected with the same bit line BL or the supply line VL are connected with different word lines WL. Thus, the storage cell is not selected and is blocked.
    [50] Write, read and erase, which are in different operating states, are set in the supply line via different voltage levels. A ferroelectric material having a coherent field strength (EC) of approximately 30 μs / cm, and a dielectric layer 131 having a relative dielectric constant (ε r ) of approximately 20, formed similarly as described by FIG. 1 or 2. For operation of storage cell systems with ferroelectric transistors, the following levels are suitable:
    [51] Reading: + 0.5 V
    [52] Record: + 3 V
    [53] Elimination:-3 V
    权利要求:
    Claims (13)
    [1" claim-type="Currently amended] In ferroelectric transistors,
    Two source / drain regions 12 are provided in the semiconductor substrate 11,
    A first gate intermediate layer 13 and a first gate electrode 14 are disposed on the surface of the semiconductor substrate 11 between the source / drain regions, the first gate intermediate layer 13 being at least one Ferroelectric layer 132,
    In the direction of the connection line between the source / drain region 12, between the source / drain region 12, next to the first gate intermediate layer 13, A second gate electrode 17 is disposed, the second gate intermediate layer 16 comprises a dielectric layer,
    The first gate electrode (14) and the second gate electrode (17) are connected to each other via a diode structure.
    [2" claim-type="Currently amended] The method of claim 1,
    The second gate intermediate layer 16 and the second gate electrode 17 are each composed of two substructures, the substructures being arranged symmetrically with respect to the first gate intermediate layer 13,
    A ferroelectric transistor, characterized in that the two partial structures of the second gate electrode (17) are electrically connected to each other.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    And the first gate intermediate layer (13) comprises a dielectric layer (131) disposed between the surface of the semiconductor substrate (11) and the ferroelectric layer (132).
    [4" claim-type="Currently amended] The method of claim 3, wherein
    And a dielectric layer (26) through which the dielectric layer (26) of the first gate intermediate layer and the dielectric layer (26) of the second gate intermediate layer are formed.
    [5" claim-type="Currently amended] The method according to any one of claims 1 to 4,
    A ferroelectric transistor, characterized in that the first gate electrode (14) and / or the second gate electrode (17) is part of the diode structure.
    [6" claim-type="Currently amended] The method of claim 5,
    The first gate electrode 14 comprises polycrystalline silicon doped with a first conductivity type,
    The second gate electrode 17 comprises polycrystalline silicon doped in a second conductivity type opposite to the first conductivity type,
    A ferroelectric transistor, characterized in that the first gate electrode (14) is adjacent to the second gate electrode (17).
    [7" claim-type="Currently amended] The method according to any one of claims 1 to 6,
    A ferroelectric transistor, characterized in that an auxiliary layer (15) is provided between the ferroelectric layer (132) and the first gate electrode (14).
    [8" claim-type="Currently amended] The method according to any one of claims 1 to 7,
    The first gate interlayer comprises CeO 2 , ZrO 2 or Y 2 O 3 , SiTiO 3 ,
    The second gate intermediate layer 16 comprises SiO 2 , CeO 2 , ZrO 2 or SiTiO 3 ,
    The ferroelectric layer 132 comprises strontium-bismuth-tantalate (SBT), lead-zirconium-titanate (PZT), lithium-nibium acid salt (LiNbO 3 ) or barium-strontium-titanate (BST)
    A ferroelectric transistor, characterized in that the semiconductor substrate (11) comprises single crystal silicon.
    [9" claim-type="Currently amended] A storage cell system comprising storage cells each having one ferroelectric transistor (FT) according to any one of claims 1 to 8.
    [10" claim-type="Currently amended] The method of claim 9,
    A word line WL, a bit line BL and a supply line VL are provided, the word line WL traversing the supply line and the bit line,
    Each storage cell comprises a selection transistor (AT) with a control electrode, in addition to the ferroelectric transistor (FT),
    A ferroelectric transistor FT of one of said storage cells is connected between adjacent bit lines BL, respectively,
    The selection transistor AT is connected between the second gate electrode of the ferroelectric transistor FT and the supply voltage line VL,
    The control electrode of said select transistor (AT) is connected with one of said word lines (WL).
    [11" claim-type="Currently amended] In the method of manufacturing a ferroelectric transistor,
    Providing a dielectric layer 26, a ferroelectric layer 23 and a first electrode layer 24 ′ on the surface of the semiconductor substrate 21,
    A first gate electrode is formed by having the first electrode layer 24 ′ and the ferroelectric layer 23 in common structure,
    The second electrode layer 27 'is deposited and a second gate electrode 27 is formed adjacent to the first gate electrode 24 and covering the first gate electrode 24 on the side; The second electrode layer 27 'is structured,
    The material of the first gate electrode 24 and the second gate electrode 27 is matched with each other such that the second gate electrode 24 and the second gate electrode 27 form a diode structure. How to feature.
    [12" claim-type="Currently amended] In the method of manufacturing a ferroelectric transistor,
    Depositing a first gate intermediate layer 26, a ferroelectric layer 23 and a first electrode layer 24 ′ on the surface of the semiconductor substrate 21,
    The first electrode layer 24 ′, the ferroelectric layer 23 and the first gate intermediate layer 26 are commonly structured and a first gate electrode 24 is formed,
    Forming a second gate intermediate layer 16 comprising a dielectric layer on the side of the first gate intermediate layer 26,
    The second electrode layer such that a second electrode layer 27 ′ is deposited, adjacent to the first gate electrode 24, and a second gate electrode 27 is formed which covers the first gate electrode on the side. This structured step,
    The material of the first gate electrode and the second gate electrode 27 is matched with each other such that the first gate electrode 24 and the second gate electrode 27 form a diode structure. Way.
    [13" claim-type="Currently amended] The method of claim 11 or 12,
    An auxiliary layer 25 is deposited between the ferroelectric layer 23 and the first electrode layer 24 ', the auxiliary layer together with the ferroelectric layer 23 and the first electrode layer 24'. Characterized in that it is jointly structured.
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    同族专利:
    公开号 | 公开日
    WO2000014808A1|2000-03-16|
    JP2002524880A|2002-08-06|
    EP1114467B1|2006-05-24|
    US6710388B2|2004-03-23|
    CN1181558C|2004-12-22|
    DE59913465D1|2006-06-29|
    EP1114467A1|2001-07-11|
    US20010038117A1|2001-11-08|
    KR100609183B1|2006-08-02|
    CN1325549A|2001-12-05|
    DE19840824C1|1999-10-21|
    TW439128B|2001-06-07|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-09-07|Priority to DE19840824A
    1998-09-07|Priority to DE19840824.2
    1999-07-05|Application filed by 추후제출, 인피니언 테크놀로지스 아게
    2001-08-09|Publication of KR20010074987A
    2006-08-02|Application granted
    2006-08-02|Publication of KR100609183B1
    优先权:
    申请号 | 申请日 | 专利标题
    DE19840824A|DE19840824C1|1998-09-07|1998-09-07|Ferroelectric transistor especially for a non-volatile memory cell|
    DE19840824.2|1998-09-07|
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